Field of the Invention
The present invention relates to a thin film transistor, and more particularly, to a thin film transistor used as a switching element of a display device.
Discussion of the Related Art
A thin film transistor has been widely used as a switching device of a display device such as a liquid crystal display device and an organic light emitting device.
The thin film transistor includes a gate electrode, an active layer, a source electrode, and a drain electrode. This thin film transistor may be divided into a staggered structure and a coplanar structure depending on arrangement of the electrodes.
In the staggered structure, the gate electrode and the source/drain electrodes are arranged down and up with reference to the active layer, and in the coplanar structure, the gate electrode and the source/drain electrodes are together arranged on the active layer.
Hereinafter, the thin film transistor according to the related art will be described with reference to the accompanying drawing.
FIG. 1a is a cross-sectional view illustrating a thin film transistor substrate of a coplanar structure according to the related art.
As shown in FIG. 1a, the thin film transistor substrate of the coplanar structure according to the related art includes a substrate 10, a buffer layer 20, an active layer 30, a gate insulating film 40, a gate electrode 50, an insulating interlayer 60, a source electrode 70a, a drain electrode 70b, a passivation film 80, and a pixel electrode 90.
Although glass is mainly used as the substrate 10, a transparent plastic, which may be bent, may be used as the substrate 10.
The buffer layer 20 is formed on the substrate 10, and serves to prevent a material contained on the substrate 10 from being diffused to the active layer 30 during a deposition process of high temperature.
The active layer 30 is formed on the buffer layer 20.
The gate insulating film 40 is formed on the active layer 30 to insulate the gate electrode 50 from the active layer 30.
The gate electrode 50 is formed on the gate insulating film 40.
The insulating interlayer 60 is formed on the entire surface of the substrate including the gate electrode 50. However, since the insulating interlayer 60 includes a first contact hole CH1 in a predetermined area, one end area and the other end area of the active layer 30 are exposed by the first contact hole CH1.
The source electrode 70a and the drain electrode 70b are formed on the insulating interlayer 60. Particularly, the source electrode 70a and the drain electrode 70b are connected with the exposed one end area and the exposed other end area of the active layer 30 through the first contact hole CH1.
The passivation film 80 is formed on the entire surface of the substrate including the source electrode 70a and the drain electrode 70b. However, since the passivation film 80 includes a second contact hole CH2 in a predetermined area, a predetermined area of the drain electrode 70b is exposed by the second contact hole CH2.
The pixel electrode 90 is formed on the passivation film 80. Particularly, the pixel electrode 90 is connected with the exposed predetermined area of the drain electrode 70b through the second contact hole CH2.
However, the aforementioned thin film transistor substrate of the coplanar structure according to the related art has a problem as follows.
The active layer 30 is exposed to light entering from the lower portion of the substrate 10, whereby reliability of the active layer 30 is deteriorated as time passes.
FIG. 1b is a cross-sectional view illustrating a thin film transistor substrate of a staggered structure according to the related art.
As shown in FIG. 1b, the thin film transistor substrate of the staggered structure according to the related art includes a substrate 10, a gate electrode 50, a gate insulating film 40, an active layer 30, a source electrode 70a, a drain electrode 70b, a passivation film 80, and a pixel electrode 90.
The gate electrode 50 is formed on the substrate 10.
The gate insulating film 40 is formed on the gate electrode 50 and insulates the gate electrode 50 from the active layer 30.
The active layer 30 is formed on the gate insulating film 40.
The source electrode 70a and the drain electrode 70b are formed on the active layer 30. In more detail, the source electrode 70a is formed on one end area of the active layer 30, and the drain electrode 70b is formed on the other end area of the active layer 30.
The passivation film 80 is formed on the entire surface of the substrate including the source electrode 70a and the drain electrode 70b. However, since the passivation film 80 is provided with a second contact hole CH2 in a predetermined area, a predetermined area of the drain electrode 70b is exposed by the second contact hole CH2.
The pixel electrode 90 is formed on the passivation film 80. Particularly, the pixel electrode 90 is connected with the predetermined area of the exposed drain electrode 70b through the second contact hole CH2.
However, the thin film transistor substrate of the staggered structure according to the related art has problems as follows.
The gate electrode 50 is formed with a big size to prevent light entering from the lower portion of the substrate 10 from being irradiated to the active layer 30. In this case, as the size of the gate electrode 50 is increased, there may be restriction in designing the thin film transistor. Also, as the size of the gate electrode 50 is increased, parasitic capacitance between the gate electrode 50 and the source electrode 70a and between the gate electrode 50 and the drain electrode 70b may be increased, whereby high speed driving of the device may be deteriorated.